The present invention deals with memory subsystems for computer systems, and more specifically with memory subsystems utilizing a combination of Read-Only Memory (ROM) and Random Access Memory (RAM) Arrays.
Memory technology has focused on the development of larger and faster discrete RAM or ROM arrays. When used in specific computer applications each type of array has inherent disadvantages. RAM arrays take up substantially more room than ROM arrays thus making it difficult to integrate a large RAM array in a very-large-scale-integration (VLSI) computer chip. RAM arrays are also volatile, thus requiring the additional cost of providing refresh media. ROM arrays are non-volatile, but their contents cannot be easily changed. Thus, applications using ROM arrays to store a control program inherently incur a higher cost in implementing changes to the code, which might be necessary to correct problems or improve features. The higher cost comes from replacing the obsolete ROM arrays in the field with a newly coded ROM array, plus the additional cost of the obsolete inventory of ROM arrays containing the old code. Combining discrete RAM and ROM parts into a multi-chip memory subsystem offsets some of these disadvantages, but incurs a high cost in the increased memory part count and interface logic.